The present disclosure relates to Complementary Metal Oxide Semiconductor (“CMOS”) integrated circuits and, more particularly, to CMOS implementations for charge recycling in memory and logic elements.
With the advance of technology, the reduction of the supply voltage (“VDD”) has become vital to reduce dynamic power usage and to avoid reliability problems in Deep Sub-Micron (“DMS”) regimes. However, reducing VDD alone causes serious degradation to the circuit's performance. One way to maintain performance is to scale down both VDD and the threshold voltage. However, reducing the threshold voltage increases the leakage current exponentially. This problem escalates in DSM technologies.